1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device capable of suppressing latch-up generation.
2. Description of the Related Art
First, a related art semiconductor device is described. FIG. 5 is a sectional view illustrating the related art semiconductor device.
When a negative voltage surge is applied to an input pad 71, electrons serving as minority carriers in a P-type semiconductor substrate 87 may leak from an N-type diffusion region 81 in an ESD protection circuit region to the P-type semiconductor substrate 87. From the semiconductor substrate 87 into a P-type diffusion region 82 connected to a ground pad 72 the minority carriers flow and are absorbed. A horizontal length of the P-type diffusion region 82 in a direction from the ESD protection circuit to an internal circuit is sufficiently large, and hence the minority carriers are sufficiently absorbed into the P-type diffusion region 82. The minority carriers that are not absorbed into the P-type diffusion region 82 are forcibly drawn out from the semiconductor substrate 87 into an N-type diffusion region 83 connected to a power supply pad 73. The minority carriers caused by the surge to the input pad 71 are a main cause of occurrence of latch-up in the internal circuit. As described above, the minority carriers are released from the semiconductor substrate 87, with the result that the latch-up in the internal circuit is not liable to be caused (see, for example, Japanese Published Patent Application No. 2007-019345).
However, in the technology disclosed in Japanese Published Patent Application No. 2007-019345, the horizontal length of the P-type diffusion region 82 in the direction from the ESD protection circuit to the internal circuit is large, and along therewith, the area of the semiconductor device becomes larger.